1. Field of the Invention
Embodiments of the present invention relate to circuits. More specifically, embodiments of the present invention relate to a method and a circuit for protecting circuits from electrostatic discharge.
2. Related Art
A major reliability problem for many integrated circuits (ICs) is electrostatic discharge (ESD). During an ESD event, a large amount of charge is transferred from one object (such as a person, a transmission line or a piece of metal) to another (such as an IC) in a relatively short period of time, which results in a peak current that can cause significant damage to the IC. For example, ESD damage can include: gate-oxide breakdown, void formation in the gate oxide, and/or melting and vaporization of interconnects. Note that a common model used for testing the resilience of an IC to an ESD event is the human body model in which the IC under test has to withstand a peak current of 1.3 A with a rise time of 10-30 ns. Another widely used ESD requirement is the ability of ICs to withstand 2000 V on any pin.
FIG. 1 presents a block diagram illustrating an existing interface circuit 100, such as an input/output circuit. In this circuit, ESD may be injected via input pad 110. While such an event can damage either or both of transistors 112, n-type pull-down transistor 112-2 is typically more sensitive to ESD. This transistor is further described in FIG. 2, which presents a block diagram illustrating parasitic effects in an existing interface circuit 200. Note that there are two ‘parasitic’ devices in this circuit associated with n-type transistor 112-2, including: the lateral npn bipolar transistor across the n-channel and the reverse diode between the drain (input pad 110) and the substrate 210 (ground), i.e., between the n+ region and the p substrate of n-type transistor 112-2.
In some existing CMOS interface circuits, the parasitic bipolar transistor associated with n-type transistor 112-2 provides ESD protection via a so-called ‘snapback’ mechanism. This is illustrated in FIG. 3, which presents a graph 300 of current 310 as a function of voltage 312 for an existing transistor. Ignoring second-order effects (such as n-gate bootstrapping), during an ESD event the snapback mechanism essentially turns on the n-channel in the n-type transistor 112-2 (FIG. 2) heavily and allows it to conduct the charge to ground. Note that the snapback mechanism provides ESD protection as long as the snap-back voltage of the n-type transistor 112-2 (FIG. 2) is smaller than the breakdown voltage VCE of the parasitic diode associated with the n-type transistor 112-2 (FIG. 2).
Unfortunately, as devices are scaled the gate-oxide thicknesses and pn-junction widths are decreased, which allows ESD events having less energy and lower voltages to damage or destroy ICs. Moreover, for technology having critical dimensions less than or equal to 250 nm, the breakdown voltage of the parasitic diodes becomes smaller than the snapback voltage, thereby turning the breakdown of the parasitic reverse pn junction into the primary ESD-protection device for n-type transistors, which is often not sufficient.
Consequently, additional protection circuits are often added around the input pad, output pad and power pads of ICs to provide effective ESD protection. For example, in typical interface circuits non-parasitic diodes are included for ESD protection. This is shown in FIG. 4, which presents a block diagram illustrating an existing interface circuit 400. Typically, diodes 410 have to be able to withstand the large currents that can occur during an ESD event (note that the diode across the n-type transistor acts as a shunt and drains all the current). However, using existing processes, the resulting diodes can occupy as much area as n-type transistor 112-2, which can significantly increase the cost of the IC.
Hence, there is a need for a circuit and a technique to protect circuits, such as interface circuits, from ESD without the above-described problems.